1. Field of the Invention
The invention relates generally to programmable logic array integrated circuits and more particularly to programmable array logic integrated circuits having improved random access memory.
2. Description of the Related Art
Commonly assigned U.S. Pat. No. 5,550,782 entitled Programmable Logic Array Integrated Circuits, which issued Aug. 27, 1996, shows programmable logic array integrated circuits which are highly modular. FIGS. 1 and 10 of that patent illustrate a multiplicity of programmable logic array modules distributed about the array in a two-dimensional pattern of rows and columns. FIGS. 11 and 20-24 of that patent illustrate the distribution of multiple dedicated random access memory blocks at various row and column locations throughout the array. FIGS. 1 and 10 of that patent also illustrate a plurality of global horizontal and global vertical conductors which extend along what shall be referred to herein as a vertical dimension between respective columns of modules and/or memory blocks and what shall be referred to herein as in a horizontal direction between respective rows of modules and/or memory blocks. The programmable logic modules and the random access memory blocks can be programmably connected to the global horizontal or to the global vertical conductors. Moreover, each module has a local interface to adjacent global conductors, and each random access memory block also has a local interface to adjacent global conductors.
U.S. Pat. No. 4,870,302 entitled Configurable Electrical Circuit Having Configurable Logic Elements And Configurable Elements, which is assigned to Xilinx, Inc., issued on Sep. 26, 1989. FIGS. 3A-3D of that patent show the use of a 16 bit random access memory as configurable logic elements which can be programmed to produce a logical function. FIG. 4A of that patent illustrates the distribution of a plurality of random access memory configurable logic elements in a two-dimensional array about the configurable electrical circuit.
The application note from Xilinx, Inc. entitled, XC4000 Series Field Programmable Gate Arrays, dated Sep. 18, 1996 discloses the implementation of either single-port or dual-port edge-triggered RAM and the implementation of level-sensitive single port RAM from configurable logic blocks in a field programmable gate array.
The application note by AT&T Microelectronics dated December 1995 entitled ORCA FPGAs Excel in Multiplexing and On-Chip SRAM Applications, discloses the use of look-up tables (LUTs) in a field programmable gate array (FPGA) to implement static random access memory (SRAM) blocks or read only memory (ROM) blocks. The note discloses, for example, how a single logic element, referred to as a programmable function unit or PFU, can be used to implement one 16.times.4 SRAM block or two 16.times.2 SRAM blocks with the remainder of the PFU used for random logic. T. Ngai, et al., in A New Generation of ORCA FPGA with Enhanced Features and Performance, IEEE 1996 Custom Integrated Circuits Conference, discloses the use of LUTs in PFUs to implement synchronous 16.times.4 memory and to implement synchronous 16.times.2 dual-port memory.
Increasingly, there are applications such as networking, for instance, that call for random access memory that is both "shallow" and "wide." While random access memory in programmable logic arrays as described above generally has been available, there is a need for more efficient use of array resources in providing such shallow and wide memory. For example, the random access memory array blocks disclosed in U.S. Pat. No. 5,550,782 are relatively "deep." For example, a 256.times.8 memory block is 256 bits deep and 8 bits wide, and digital information typically is read or written 8 bits at a time. Since networking and communications applications often require primarily shallow and wide memory, a significant portion of a memory block often remains unused in these applications, and the space occupied by that block, which otherwise could be used for programmable logic, is wasted. Although smaller memory blocks can be produced by configuring one or more look-up tables as random access memory, as described in the references discussed above for example, these memory blocks typically are produced by consuming LUT resources that otherwise could be programmed to provide logic finctions.
Thus, there has been a need for a programmable array logic circuit which more efficiently uses array resources in providing random access memory blocks. In particular, there has been a need for more efficient implementation of shallow and wide memory. The present invention meets this need.